1. Field
Exemplary embodiments of the present invention relate to impedance matching in a system and package including a plurality of chips.
2. Description of the Related Art
A variety of semiconductor chips implemented as integrated chips, such as a CPU, a memory, and a gate array, are assembled into various electronic products such as a personal computer, a server, and a workstation. In most cases, a semiconductor chip includes a receiver circuit configured to receive various signals through an input pad and an output circuit configured to provide an internal signal through an output pad.
As the operation speed of electronic products increases, the swing width of signals interfaced between semiconductor chips has been gradually reduced. The swing width is reduced to minimize a delay time required for signal transmission. However, as the swing width is reduced, the influence of external noise increases, and signal reflection caused by impedance mismatching becomes severe at the interface terminal. The impedance mismatching occurs due to variations in external noise, power supply voltage, operation temperature, or fabrication process. When the impedance mismatching occurs, transmitting data at high speed may be difficult, and data outputted from a data output terminal of a semiconductor device may be distorted. Therefore, when a semiconductor chip receives the distorted output signal through an input terminal, a setup/hold fail or determination mistake for input level may frequently occur.
A memory chip implementing high operation speed employs an impedance matching circuit within the integrated circuit chip. The impedance matching circuit is called an on-die termination circuit. When data is inputted to the integrated circuit chip through an I/O channel, the impedance matching circuit performs a termination operation of the I/O channel to match impedance.
FIG. 1 illustrates a termination circuit provided for impedance matching of a semiconductor chip.
The termination circuit 110 includes a plurality of pull-up resistors 111 to 114, a plurality of pull-down resistors 115 to 118, and a plurality of switches SW1 to SW8 configured to turn on/off the resistors. When data (or a signal) is inputted through an I/O pad 101, some or all of the pull-up resistors 111 to 114 and some or all of the pull-down resistors 115 to 118 are turned on. As a result, the impedance of an I/O channel coupled to the I/O pad 101 is matched. As a result of the impedance matching, an input buffer 102 may recognize the data correctly.
During the termination operation, the number of resistors to be turned on among the plurality of pull-up resistors 111 to 114 and the plurality of pull-down resistors 115 to 118 changes depending on a termination resistance value. The termination resistance value is decided by the initial setting of the semiconductor chip or by an operation of a calibration circuit inside the semiconductor chip.
Additionally, a plurality of memory chips may be stacked within one package and share an I/O channel.